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| Authors: | Martin Naedele, Lothar Thiele, Michael Eisenring |
| Group: | Computer Engineering |
| Type: | Inproceedings |
| Title: | Characterising Variable Task Releases and Processor Capacities |
| Year: | 1999 |
| Month: | July |
| Pub-Key: | NTE99 |
| Book Titel: | 14th IFAC World Congress 1999 |
| Abstract: | For the schedulability analysis of hard real-time systems it is important to use task and resource models that appropriately capture the characteristics of the underlying system. In this paper a general task model, the variable task model, most appropriate for tasks with bursty release characteristics, is formalized. Also, a new processor model, the variable processor model, is suggested which allows to account for dead time and variable processing speed. It is shown how worst case bounds on task response time can be calculated. A general schedulability test is derived. |
| Remarks: | 14th IFAC World Congress 1999, Beijing, July 1999 |
| Location: | Beijing |
| Resources: | [BibTeX] [Paper as PDF] |
